1. Technical Field
The present invention relates to estimating a terminal capacitance and for characterizing a circuit. In particular, the present invention relates to estimating a terminal capacitance at a given operation point.
2. Background Information
The operation of many electronic design automation tools, such as tools for logic synthesis or timing analysis, is based on capacitance values associated with pins or terminals of cells of a digital circuit. In conventional electronic design automation tools, the capacitance associated with a pin or a terminal of a cell is set equal to one of a plurality of predetermined capacitance values that have been previously established by pre-characterizing the cell. The predetermined capacitance value may correspond, e.g., to the maximum and minimum effective capacitance of the pin or terminal in a relevant range of operation parameters. For example, to establish that timing constraints are met, many conventional timing analysis tools employ the maximum capacitance value and the minimum capacitance value to determine signal propagation times in a data path or a clock path, respectively. However, such conventional methods for determining signal propagation times, in which capacitance values are approximated by minimum or maximum capacitance values in the relevant operation range, frequently provide excessively pessimistic predictions for the performance characteristics of a digital circuit, such as setup slack.